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1 ds05-11217-1e fujitsu semiconductor data sheet memory cmos 4m 64 fast page mode dram module mb8504d064aa-60/-70 cmos 4m 64 bit fast page mode dram module n description the fujitsu mb8504d064aa is a fully decoded, cmos dynamic random access memory (dram) module consisting of sixteen mb8117400a devices. the mb8504d064aa is optimized for those applications requiring high speed, high performance and large memory storage. the operation and electrical characteristics of the mb8504d064aa are the same as the mb8117400a which features fast page mode operation. for ease of memory expansion, the mb8504d064aa is offered in an 168-pad dual in-line memory module package (dimm). n absolute maximum ratings (see note) note: permanent device damage may occur if the above absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. parameter symbol value unit supply voltage v cc ?.5 to +7.0 v input voltage v in ?.5 to +7.0 v output voltage v out ?.5 to +7.0 v short circuit output current i out 50 ma power dissipation p d 18 w storage temperature t stg ?5 to +125 c this device contains circuitry to protect the inputs against damage due to high static voltages or electric ?lds. however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit.
2 mb8504d064aa-60/MB8504D064AA-70 n product line & features n package parameter mb8504d064aa-60 MB8504D064AA-70 ras access time 60 ns max. 70 ns max. random cycle time 110 ns max. 130 ns max. address access time 35 ns max. 40 ns max. cas access time 20 ns min. 22 ns min. fast page mode cycle time 40 ns min. 45 ns min. power dissipation operating mode 10395 mw max. 8965 mw max. standby mode 671 mw max. 671 mw max. conformed to 8-byte dimm jedec standard organization : 4,194,304 words 64 bits module size : 1.00 (height) 5.25 (length) 0.157 (thick) memory : mb8117400a (4m 4, 2k ref.), 16 pcs tis input buffers, 3 pcs decoupling capacitors, 19 pcs 5.0 v 10% supply voltage 2,048 refresh cycles / 32.8 ms fast page operation ras only refresh/cas -before-ras refresh package and ordering information: 168-pad dimm, order as mb8504d064aa-xxdg (dg = gold pad) mds-168p-p05
3 mb8504d064aa-60/MB8504D064AA-70 fig. 1 ? block diagram dq 0 dq 1 dq 2 dq 3 i/o i/o i/o i/o chip 1 i/o i/o i/o i/o chip 2 i/o i/o i/o i/o chip 3 i/o i/o i/o i/o chip 4 i/o i/o i/o i/o chip 5 i/o i/o i/o i/o chip 6 i/o i/o i/o i/o chip 7 cas i/o i/o i/o i/o we ras chip 0 oe a 0 a 1 -a 10 sn74abt162244 i/o i/o i/o i/o chip 9 i/o i/o i/o i/o chip 10 i/o i/o i/o i/o chip 11 i/o i/o i/o i/o chip 8 i/o i/o i/o i/o chip 12 i/o i/o i/o i/o chip 13 i/o i/o i/o i/o chip 14 i/o i/o i/o i/o chip 15 a 0 a 1 -a 10 ras 0 cas 0 we 0 oe 0 dq 4 dq 5 dq 6 dq 7 cas 1 dq 8 dq 9 dq 10 dq 11 dq 12 dq 13 dq 14 dq 15 cas 2 dq 16 dq 17 dq 18 dq 19 dq 20 dq 21 dq 22 dq 23 cas 3 dq 24 dq 25 dq 26 dq 27 dq 28 dq 29 dq 30 dq 31 v cc v ss c 0 -c 18 chip 0 - 18 pde v cc or v ss pd 1 -pd 8 (drivers, chip 16 , 17 , 18 ) a 0 a 1 -a 10 cas we ras oe cas we ras oe cas we ras oe a 0 a 1 -a 10 cas we ras oe a 0 a 1 -a 10 cas we ras oe a 0 a 1 -a 10 cas we ras oe a 0 a 1 -a 10 cas we ras oe a 0 a 1 -a 10 a 0 a 1 -a 10 cas we ras oe a 0 a 1 -a 10 a 0 a 1 -a 10 cas we ras oe cas we ras oe cas we ras oe a 0 a 1 -a 10 cas we ras oe a 0 a 1 -a 10 cas we ras oe a 0 a 1 -a 10 cas we ras oe a 0 a 1 -a 10 cas we ras oe a 0 a 1 -a 10 a 0 a 1 -a 10 dq 32 dq 33 dq 34 dq 35 ras 2 cas 4 we 2 oe 2 dq 36 dq 37 dq 38 dq 39 cas 5 dq 40 dq 41 dq 42 dq 43 dq 44 dq 45 dq 46 dq 47 cas 6 dq 48 dq 49 dq 50 dq 51 dq 52 dq 53 dq 54 dq 55 cas 7 dq 56 dq 57 dq 58 dq 59 dq 60 dq 61 dq 62 dq 63 b 0
4 mb8504d064aa-60/MB8504D064AA-70 n pin assignments (continued) pin no. mb8504d064aa pin no. mb8504d064aa pin no. mb8504d064aa pin no. mb8504d064aa 1v ss 36 a 6 71 dq 27 106 nc 2dq 0 37 a 8 72 dq 28 107 v ss 3dq 1 38 a 10 73 v cc 108 nc 4dq 2 39 nc 74 dq 29 109 nc 5dq 3 40 v cc 75 dq 30 110 v cc 6v cc 41 nc 76 dq 31 111 nc 7dq 4 42 nc 77 nc 112 cas 1 8dq 5 43 v ss 78 v ss 113 cas 3 9dq 6 44 oe 279pd 1 114 nc 10 dq 7 45 ras 280pd 3 115 nc 11 nc 46 cas 481pd 5 116 v ss 12 v ss 47 cas 682pd 7 117 a 1 13 dq 8 48 we 283id 0 118 a 3 14 dq 9 49 v cc 84 v cc 119 a 5 15 dq 10 50 nc 85 v ss 120 a 7 16 dq 11 51 nc 86 dq 32 121 a 9 17 dq 12 52 dq 16 87 dq 33 122 nc 18 v cc 53 dq 17 88 dq 34 123 nc 19 dq 13 54 v ss 89 dq 35 124 v cc 20 dq 14 55 dq 18 90 v cc 125 nc 21 dq 15 56 dq 19 91 dq 36 126 b 0 22 nc 57 dq 20 92 dq 37 127 v ss 23 v ss 58 dq 21 93 dq 38 128 nc 24 nc 59 v cc 94 dq 39 129 nc 25 nc 60 dq 22 95 nc 130 cas 5 26 v cc 61 nc 96 v ss 131 cas 7 27 we 062nc 97dq 40 132 pde 28 cas 063 nc 98dq 41 133 v cc 29 cas 264 nc 99dq 42 134 nc 30 ras 065dq 23 100 dq 43 135 nc 31 oe 0 66 nc 101 dq 44 136 dq 48 32 v ss 67 dq 24 102 v cc 137 dq 49 33 a 0 68 v ss 103 dq 45 138 v ss 34 a 2 69 dq 25 104 dq 46 139 dq 50 35 a 4 70 dq 26 105 dq 47 140 dq 51
5 mb8504d064aa-60/MB8504D064AA-70 (continued) pin no. mb8504d064aa pin no. mb8504d064aa pin no. mb8504d064aa pin no. mb8504d064aa 141 dq 52 148 nc 155 dq 59 162 v ss 142 dq 53 149 dq 55 156 dq 60 163 pd 2 143 v cc 150 nc 157 v cc 164 pd 4 144 dq 54 151 dq 56 158 dq 61 165 pd 6 145 nc 152 v ss 159 dq 62 166 pd 8 146 nc 153 dq 57 160 dq 63 167 id 1 147 nc 154 dq 58 161 nc 168 v cc
6 mb8504d064aa-60/MB8504D064AA-70 n pin descriptions n presence detect (pd)/id definition n capacitance (t a = 25 c, f = 1 mhz, v cc = +5.0 v) symbol function input/output pin count a 0 to a 10 , b 0 address input input 12 ras 0 and ras 2 row address strobe input 2 cas 0 to cas 7 column address strobe input 8 we 0 and we 2 write enable input 2 oe 0 and oe 2 output enable input 2 dq 0 to dq 63 data-input/data-output input/output 64 pd 1 to pd 8 presence detect output 8 id 0 to id 1 id bit output 2 pde presence detect enable input 1 v cc power supply 16 v ss ground 16 nc no connection 35 symbol mb8504d064aa-60 MB8504D064AA-70 description of pd/id pd 1 h h module density, dram organization and addressing; module density: 32mb, number of bank: 1 bank module con?uration: 4m 64 mounted dram con?uration: 4m 4 dram address (row/column): 11/11 pd 2 hh pd 3 ll pd 4 hh pd 5 l l edo detection; fast page mode : pd 5 = l pd 6 h l module speed; 60 ns : pd 6 = h, pd 7 = h 70 ns : pd 6 = l, pd 7 = h pd 7 hh pd 8 h h ecc / parity detection; (parity) : pd 8 = h id 0 l l module type; 64 (parity) : id 0 = l id 1 l l refresh mode; normal refresh : id 1 = l parameter symbol min. max. unit input capacitance, (address) c in1 ?0pf input capacitance, (ras )c in2 ?5pf input capacitance, (cas , we , oe )c in3 ?0pf i/o capacitance, (dq) c dq ?0pf
7 mb8504d064aa-60/MB8504D064AA-70 n recommended operating conditions (referenced to v ss ) note: *undershoots of up to ?.5 volts with a pulse width not exceeding 10 ns are acceptable. n dc characteristics (recommended operating conditions unless otherwise noted.) notes: *1. referenced to v ss . *2. i cc depends on the output load conditions and cycle rate. the speci? values are obtained with the output open. i cc depends on the number of address change as ras = v il and cas = v ih , v il > ?.3 v. i cc1 , i cc3 , i cc4 and i cc5 are speci?d at one time of address change during ras = v il and cas = v ih . parameter symbol min. typ. max. unit supply voltage v cc 4.5 5.0 5.5 v ground v ss ?v input high voltage, all inputs v ih 2.4 6.0 v input low voltage, all inputs* v il ?.3 0.8 v ambient temperature t a 070 c parameter test condition symbol min. max. unit output high voltage* 1 i oh = ? ma v oh 2.4 v output low voltage* 1 i ol = 4.2 ma v ol 0.4 v input leakage current 0 v v in 5.5 v, 4.5 v v cc 5.5 v, v ss = 0 v, all other pins not under test = 0 v i i (l) ?0 50 m a ?0 10 output leakage current 0 v v out 5.5 v, 4.5 v v cc 5.5 v, data out disabled i o(l) ?0 10 m a operating current* 2 (average power supply current) mb8504d064aa-60 ras & cas cycling, t rc = min. i cc1 1890 ma MB8504D064AA-70 1630 standby current* 2 (power supply current) ttl level ras = cas = pde =v ih i cc2 122 ma cmos level ras = cas = pde 3 v cc ?.2 v 106 refresh current #1* 2 (average power supply current) mb8504d064aa-60 cas = v ih , ras = cycling, t rc = min. i cc3 1890 ma MB8504D064AA-70 1630 fast page mode current* 2 mb8504d064aa-60 ras = v il , cas = cycling, t rc = min. i cc4 1390 ma MB8504D064AA-70 1220 refresh current #2* 2 (average power supply current) mb8504d064aa-60 ras = cycling, cas -before- ras , t rc = min. i cc5 1890 ma MB8504D064AA-70 1630 ras others
8 mb8504d064aa-60/MB8504D064AA-70 n ac characteristics (at recommended operating conditions unless otherwise noted.) notes 1, 2, 3 (continued) no. parameter symbol mb8504d064aa-60 MB8504D064AA-70 unit notes min. max. min. max. 1 time between refresh t ref 32.8 32.8 ms 2 random read/write cycle time t rc 110 130 ns 3 read-modify-write cycle time t rwc 150 174 ns 4 access time from ras t rac 60 70 ns 4, 7 5 access time from cas t cac 20 22 ns 5, 7 6 column address access time t aa 35 40 ns 6, 7 7 output hold time t oh 5?ns 8 output buffer turn on delay time t on 2?ns 9 output buffer turn off delay time t off ?0?2ns8 10 transition time t t 216216ns 11 ras precharge time t rp 40?0ns 12 ras pulse width t ras 60 100000 70 100000 ns 13 ras hold time t rsh 20?2ns 14 cas to ras precharge time t crp 5?ns 15 ras to cas delay time t rcd 18 40 18 48 ns 9, 10 16 cas pulse width t cas 15?7ns 17 cas hold time t csh 58?8ns 18 cas precharge time (c-b-r refresh) t cpn 10?0ns17 19 row address setup time t asr 5?ns 20 row address hold time t rah 8?ns 21 column address setup time t asc 0?ns 22 column address hold time t cah 15?5ns 23 column address hold time from ras t ar 33?3ns 24 ras to column address delay time t rad 13 25 13 30 ns 11 25 column address to ras lead time t ral 35?0ns 26 column address to cas lead time t cal 30?5ns 27 read command setup time t rcs 0?ns 28 read command hold time referenced to ras t rrh 22ns12 29 read command hold time referenced to cas t rch 0?ns12 30 write command setup time t wcs 0?ns 13, 18
9 mb8504d064aa-60/MB8504D064AA-70 (continued) no. parameter symbol mb8504d064aa-60 MB8504D064AA-70 unit notes min. max. min. max. 31 write command hold time t wch 15?5ns 32 write command hold time from ras t wcr 33?3ns 33 we pulse width t wp 15?5ns 34 write command to ras lead time t rwl 20?2ns 35 write command to cas lead time t cwl 15?7ns 36 d in setup time t ds 22ns 37 d in hold time t dh 20?0ns 38 data hold time from ras t dhr 35?5ns 39 ras to we delay time t rwd 78?0ns18 40 cas to we delay time t cwd 35?9ns18 41 column address to we delay time t awd 50?7ns18 42 ras precharge time to cas active time (refresh cycles) t rpc 3?ns 43 cas setup time (c-b-r refresh) t csr 5?ns 44 cas hold time (c-b-r refresh) t chr 8 10 ns 45 we setup time from ras t wsr 5?ns 46 we hold time from ras t whr 8?ns 47 access time from oe t oea ?0?2ns7 48 output buffer turn off delay from oe t oez ?0?2ns8 49 oe to ras lead time for valid data t oel 10?2ns 50 oe hold time referenced to we t oeh 5?ns14 51 oe to data in delay time t oed 20?2ns 52 cas to data in delay time t cdd 20?2ns 53 d in to cas delay time t dzc 22ns15 54 d in to oe delay time t dzo 22ns15 55 fast page mode ras pulse width t rasp 100000 100000 ns 56 fast page mode read/write cycle time t pc 40?5ns 57 fast page mode read-modify-write cycle time t prwc 80?9ns 58 access time from cas precharge t cpa 40 45 ns 7,16 59 fast page mode cas precharge time t cp 10?0ns 60 fast page mode ras hold time from cas precharge t rhcp 40?5ns 61 fast page mode cas precharge to we delay time t cpwd 55?2ns18
10 mb8504d064aa-60/MB8504D064AA-70 notes: 1. an initial pause (ras = cas =v ih ) of 200 m s is required after power-up followed by any eight ras -only cycles before proper device operation is achieved. if an internal refresh counter is used, a minimum of eight cas -before-ras initialization cycles are required instead of eight ras cycles. 2. ac characteristics assume t t = 5 ns. 3. v ih (min.) and v il (max.) are reference levels for measuring the timing of input signals. transition times are measured between v ih (min.) and v il (max.). 4. assumes that t rcd t rcd (max.), t rad t rad (max.). if t rcd is greater than the maximum recommended value shown in this table, t rac will be increased by the amount that t rcd exceeds the value shown. 5. if t rcd 3 t rcd (max.), t rad 3 t rad (max.), and t asc 3 t aa ?t cac ?t t , access time is t cac . 6. if t rad 3 t rad (max.) and t asc t aa ?t cac ?t t , access time is t aa . 7. measured with a load equivalent to two ttl loads and 100 pf. 8. t off and t oez are speci?d that output buffer change to high impedance state. 9. operation within the t rcd (max.) limit ensures that t rac (max.) can be met. t rcd (max.) is speci?d as a reference point only; if t rcd is greater than the speci?d t rcd (max.) limit, access time is controlled exclusively by t cac or t aa . 10. t rcd (min.) = t rah (min.)+ 2 t t + t asc (min.). 11. operation within the t rad (max.) limit ensures that t rac (max.) can be met. t rad (max.) is speci?d as a reference point only; if t rad is greater than the speci?d t rad (max.) limit, access time is controlled exclusively by t cac or t aa . 12. either t rrh or t rch must be satis?d for a read cycle. 13. t wcs is speci?d as a reference point only. if t wcs 3 t wcs (min.) the data output pin will remain high-z state through entire cycle. 14. assumes that t wcs < t wcs (min.). 15. either t dzc or t dzo must be satis?d. 16. t cpa is access time from the selection of a new column address (caused by changing cas from ? to ??. therefore, if t cp become long, t cpa also become longer than t cpa (max.). 17. assumes that cas -before-ras refresh. 18. t wcs , t cwd , t rwd , t awd , and t cpwd are not restrictive operating parameters. they are included in the data sheet as an electrical characteristic only. if t wcs 3 t wcs (min.), the cycle is an early write cycle and dout pin will maintain high impedance state throughout the entire cycle. if t cwd 3 t cwd (min.), t rwd 3 t rwd (min.) , t awd 3 t awd (min.), and t cpwd 3 t cpwd (min.), the cycle is a read-modify-write cycle and data from the selected cell will appear at the d out pin. if neither of the above conditions is satis?d, the cycle is a delayed write cycle and invalid data will appear the d out pin, and write operation can be executed by satisfying t rwl , t cwl , t ral and t cal speci?ations. *source: see mb8117400a data sheet for details on the electricals.
11 mb8504d064aa-60/MB8504D064AA-70 n package dimensions (suf?: dg) 5.250 .005 (133.35 0.13) 5.171 .005 (131.35 0.13) 168-pad plastic dual in-line type module (case no.: mds-168p-p05) ? 1995 fujitsu limited m168005sc dimensions in inches (millimeters) .700 .005 (17.78 0.13) 1.000 .005 (25.40 0.13) .450 .005 (11.43 0.05) .050 .001 (1.27 0.03) 1.450 .002 (36.83 0.05) 2.150+.002 (54.61+0.05) .118 .005 (3.00 0.13) .157 max. (4.00 max.) 4.550 .005 (115.57 0.13) .157 .005 (4.00 0.13) 1 2.586 .005 (65.68 0.13) 5.014 .004 (127.35 0.10) 1.700 .005 (43.18 0.13) c l .125 .005 (3.17 0.13) detail a detail b detail c detail a detail b detail c c l c l .157 min. (4.00 min.) ?.118 .002 (?3.00 0.05) .250 .005 (6.35. 0.13) .128 .118 (3.25) (3.00) .079 .004 (2.00 0.10) .039 .002 (1.00 0.05) .250 .005 (6.35. 0.13) .039 .002 (1.00 0.05) .128 .118 (3.25) (3.00) .039 .002 (1.00 0.05) .079 .004 (2.00 0.10) .100 typ. (2.54 typ.) notches full r .118(3.00)min. 85 168 84 c l 2.625 .005 (66.68 0.13) 2.507 .005 (63.68 0.13) .050+.004 ?003 (1.27+0.10 ?.08) 0.10 max. (0.25 max.)
12 mb8504d064aa-60/MB8504D064AA-70 all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan. fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-88, japan tel: (044) 754-3753 fax: (044) 754-3329 north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, u.s.a. tel: (408) 922-9000 fax: (408) 432-9044/9045 europe fujitsu mikroelektronik gmbh am siebenstein 6-10 63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 asia paci? fujitsu microelectronics asia pte. limited #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281 0770 fax: (65) 281 0220 f9704 ? fujitsu limited printed in japan

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